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? semiconductor components industries, llc, 2006 october, 2006 ? rev. 1 1 publication order number: ncv8842/d ncv8842 1.5 a, 170 khz, buck regulator with synchronization capability the ncv8842 is a 1.5 a buck regulator ic operating at a fixed?frequency of 170 khz. the device uses the v 2 control architecture to provide unmatched transient response, the best overall regulation and the simplest loop compensation for today? s high?speed logic. the ncv8842 accommodates input voltages from 4.5 v to 40 v and contains synchronization circuitry. the on?chip npn transistor is capable of providing a minimum of 1.5 a of output current, and is biased by an external ?boost? capacitor to ensure saturation, thus minimizing on?chip power dissipation. protection circuitry includes th ermal shutdown, cycle?by?cycle current limiting and frequency foldback. features ? v 2 architecture provides ultra?fast transient response, improved regulation and simplified design ? 2.0% error amp reference voltage tolerance ? switch frequency decrease of 4:1 in short circuit conditions reduces short circuit power dissipation ? boost lead allows ?bootstrapped? operation to maximize efficiency ? sync function for parallel supply operation or noise minimization ? shutdown lead provides power?down option ? 1.0 a quiescent current during power?down ? thermal shutdown ? soft?start ? internally fused leads in so?16l package ? ncv prefix for automotive and other applications requiring site and control changes ? pb?free packages are available marking diagrams http://onsemi.com so?16 wb pw suffix case 751ag 1 16 ncv8842 awlyywwg 1 16 18?lead dfn mn suffix case 505 1 ncv8842 awlyyww 1 18 18 a = assembly location l, wl = wafer lot y, yy = year w, ww = work week e = automotive grade or g = pb?free package (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ordering information
ncv8842 http://onsemi.com 2 figure 1. application diagram, 4.5 v ? 16 v to 3.3 v @ 1.0 a converter d2 vout (3.3 v) vin (7 v to 16 v) d1 r2 127 r3 205 + u1 nc nc nc nc sync nc nc nc vsw shdnb nc vfb vc boost vin gnd epad + r6 10k shdnb sync c3 100 f l1 27 h c1 1 f ncv8842 c4 0.1 f c5 0.1 f c2 330 f maximum ratings* rating value unit peak transient voltage (31 v load dump @ v in = 14 v) 45 v operating junction temperature range, t j ?40 to 150 c lead temperature soldering: reflow: (note 1) 240 peak (note 2) c storage temperature range, t s ?65 to +150 c esd (human body model) (machine model) (charge device model) 2.0 200 >1.0 kv v kv package thermal resistance so?16 junction?to?case, r jc so?16 junction?to?ambient, r ja 18?lead dfn junction?to?ambient, r ja 16 57 35 c/w c/w c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *the maximum package power dissipation must be observed. 1. 60 second maximum above 183 c. 2. ?5 c/0 c allowable conditions. maximum ratings (voltages are with respect to gnd) pin name v max v min i source i sink v in (dc)* 40 v ?0.3 v n/a 4.0 a boost 40 v ?0.3 v n/a 100 ma v sw 40 v ?0.6 v/?1.0 v, t < 50 ns 4.0 a 10 ma v c 7.0 v ?0.3 v 1.0 ma 1.0 ma shdnb 7.0 v ?0.3 v 1.0 ma 1.0 ma sync 7.0 v ?0.3 v 1.0 ma 1.0 ma v fb 7.0 v ?0.3 v 1.0 ma 1.0 ma *see table above for load dump.
ncv8842 http://onsemi.com 3 package pin description so?8 so?16 pin symbol function 1 15 boost the boost pin provides additional drive voltage to the on?chip npn power transistor. the resulting decrease in switch on voltage increases efficiency. 2 16 v in this pin is the main power input to the ic. 3 1 v sw this is the connection to the emitter of the on?chip npn power transistor and serves as the switch output to the inductor. this pin may be subjected to nega- tive voltages during switch off?time. a catch diode is required to clamp the pin voltage in normal operation. this node can stand ?1.0 v for less than 50 ns during switch node flyback. 4 2 shdnb the shutdown pin is active low and ttl compatible. the ic goes into sleep mode, drawing less than 1.0 a when the pin voltage is pulled below 1.0 v. this pin should be left floating in normal position. 5 7 sync this pin provides the synchronization input. 6 8 gnd power return connection for the ic. 7 9 v fb the fb pin provides input to the inverting input of the error amplifier. if v fb is lower than 0.29 v, the oscillator frequency is divided by four, and current limit folds back to about 1 ampere. these features protect the ic under severe over- current or short circuit conditions. 8 10 v c the v c pin provides a connection point to the output of the error amplifier and input to the pwm comparator. driving of this pin should be avoided because on?chip test circuitry becomes active whenever current exceeding 0.5 ma is forced into the ic. ? 3 ? 6, 11 ? 14 nc no connection pin connections 1 16 v fb gnd v c sync nc nc nc nc nc nc nc nc boost shdnb v in v sw 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 boost v in v in v in vsw v sw v sw shdnb nc nc v c v fb nc nc gnd nc nc sync so?16 18?lead dfn
ncv8842 http://onsemi.com 4 electrical characteristics (?40 c < t j < 125 c, 4.5 v< v in < 40 v; unless otherwise specified.) characteristic test conditions min typ max unit oscillator operating frequency ? 153 170 187 khz frequency line regulation ? ? 0.05 0.15 %/v maximum duty cycle ? 85 90 95 % v fb frequency foldback threshold ? 0.29 0.32 0.36 v pwm comparator slope compensation voltage fix v fb, v c / t on 5.0 9.0 17 mv/ s minimum output pulse width v fb to v sw ? 100 200 ns power switch current limit v fb > 0.36 v 1.6 2.3 3.0 a foldback current v fb < 0.29 v 0.9 1.5 2.1 a saturation voltage i out = 1.5 a, v boost = v in + 2.5 v 0.4 0.7 1.0 v current limit delay note 3 ? 120 160 ns error amplifier internal reference voltage ? 1.244 1.270 1.296 v reference psrr note 3 ? 40 ? db fb input bias current ? ? 0.02 0.1 a output source current v c = 1.270 v, v fb = 1.0 v 15 25 35 a output sink current v c = 1.270 v, v fb = 2.0 v 15 25 35 a output high voltage v fb = 1.0 v 1.39 1.46 1.53 v output low voltage v fb = 2.0 v 5.0 20 60 mv unity gain bandwidth note 3 ? 500 ? khz open loop amplifier gain note 3 ? 70 ? db amplifier transconductance note 3 ? 6.4 ? ma/v sync sync frequency range ? 190 ? 355 khz sync pin bias current v sync = 5.0 v ? 360 485 a sync threshold voltage ? 0.9 1.5 1.9 v shutdown shutdown threshold voltage ? 1.0 1.3 1.6 v shutdown pin bias current v shdnb = 0 v 0.14 5.00 35 a thermal shutdown overtemperature trip point note 3 175 185 195 c thermal shutdown hysteresis note 3 ? 42 ? c 3. guaranteed by design, not 100% tested in production.
ncv8842 http://onsemi.com 5 electrical characteristics (continued) (?40 c < t j < 125 c, 4.5 v< v in < 40 v; unless otherwise specified.) characteristic unit max typ min test conditions general quiescent current i sw = 0 a ? 4.0 7.5 ma shutdown quiescent current v shdnb = 0 v ? 1.0 5.0 a boost operating current v boost ? v sw = 2.5 v 6.0 15 40 ma/a minimum boost voltage note 4 ? ? 2.5 v startup voltage ? 2.2 3.3 4.4 v minimum output current ? ? 7.0 12 ma 4. guaranteed by design, not 100% tested in production. v in gnd v sw boost r s q 1.27 v v fb figure 2. block diagram + ? + ? + ? ? + + ? + ? ? + + ? thermal shutdown oscillator 1.46 v 1.3 v 5.0 a artificial ramp output driver current limit comparator frequency and current limit foldback 0.32 v pwm comparator i foldback i ref shutdown comparator 2.9 v ldo voltage regulator shdnb sync v c error amplifier shdnb
ncv8842 http://onsemi.com 6 applications information theory of operation v 2 control the ncv8842 buck regulator provides a high level of integration and high operating frequencies allowing the layout of a switch?mode power supply in a very small board area. this device is based on the proprietary v 2 control architecture. v 2 control uses the output voltage and its ripple as the ramp signal, providing an ease of use not generally associated with voltage or current mode control. improved line regulation, load regulation and very fast transient response are also major advantages. figure 3. buck converter with v 2 control. buck controller ffb v ref + duty cycle v 2 control error amplifier pwm comparator r1 oscillator ? + ? ? + v o sfb v in latch slope comp l1 c1 d1 r2 s r v c s1 as shown in figure 3, there are two voltage feedback paths in v 2 control, namely ffb(fast feedback) and sfb(slow feedback). in ffb path, the feedback voltage connects directly to the pwm comparator. this feedback path carries the ramp signal as well as the output dc voltage. artificial ramp derived from the oscillator is added to the feedback signal to improve stability. the other feedback path, sfb, connects the feedback voltage to the error amplifier whose output v c feeds to the other input of the pwm comparator. in a constant frequency mode, the oscillator signal sets the output latch and turns on the switch s1. this starts a new switch cycle. the ramp signal, composed of both artificial ramp and output ripple, eventually comes across the v c voltage, and consequently resets the latch to turn off the switch. the switch s1 will turn on again at the beginning of the next switch cycle. in a buck converter, the output ripple is determined by the ripple current of the inductor l1 and the esr (equivalent series resistor) of the output capacitor c1. the slope compensation signal is a fixed voltage ramp provided by the oscillator. adding this signal eliminates subharmonic oscillation associated with the operation at duty cycle greater than 50%. the artificial ramp also ensures the proper pwm function when the output ripple voltage is inadequate. the slope compensation signal is properly sized to serve it purposes without sacrificing the transient response speed. under load and line transient, not only the ramp signal changes, but more significantly the dc component of the feedback voltage varies proportionally to the output voltage. ffb path connects both signals directly to the pwm comparator. this allows instant modulation of the duty cycle to counteract any output voltage deviations. the transient response time is independent of the error amplifier bandwidth. this eliminates the delay associated with error amplifier and greatly improves the transient response time. the error amplifier is used here to ensure excellent dc accuracy. error amplifier the ncv8842 has a transconductance error amplifier, whose non?inverting input is connected to an internal reference voltage generated from the on?chip regulator. the inverting input connects to the v fb pin. the output of the error amplifier is made available at the v c pin. a typical frequency compensation requires only a 0.1 f capacitor connected between the v c pin and ground, as shown in figure 1. this capacitor and error amplifier?s output resistance (approximately 8.0 m ) create a low frequency pole to limit the bandwidth. since v 2 control does not require a high bandwidth error amplifier, the frequency compensation is greatly simplified. the v c pin is clamped below output high voltage. this allows the regulator to recover quickly from over current or short circuit conditions. oscillator and sync feature the on?chip oscillator is trimmed at the factory and requires no external components for frequency control. the high switching frequency allows smaller external components to be used, resulting in a board area and cost savings. the tight frequency tolerance simplifies magnetic components selection. the switching frequency is reduced to 25% of the nominal value when the v fb pin voltage is below frequency foldback threshold. in short circuit or over?load conditions, this reduces the power dissipation of the ic and external components. an external clock signal can sync the ncv8842 to a higher frequency. the rising edge of the sync pulse turns on the power switch to start a new switching cycle, as shown in figure 4. there is approximately 0.5 s delay between the rising edge of the sync pulse and rising edge of the v sw pin voltage. the sync threshold is ttl logic compatible, and
ncv8842 http://onsemi.com 7 duty cycle of the sync pulses can vary from 10% to 90%. the frequency foldback feature is disabled during the sync mode. figure 4. a ncv8842 buck regulator is synchronized to an external 350 khz pulse signal power switch and current limit the collector of the built?in npn power switch is connected to the v in pin, and the emitter to the v sw pin. when the switch turns on, the v sw voltage is equal to the v in minus switch saturation voltage. in the buck regulator, the v sw voltage swings to one diode drop below ground when the power switch turns off, and the inductor current is commutated to the catch diode. due to the presence of high pulsed current, the traces connecting the v sw pin, inductor and diode should be kept as short as possible to minimize the noise and radiation. for the same reason, the input capacitor should be placed close to the v in pin and the anode of the diode. the saturation voltage of the power switch is dependent on the switching current, as shown in figure 5. figure 5. the saturation voltage of the power switch increases with the conducting current 0 0.5 1.0 1.5 switching current (a) v in ? v sw (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 the ncv8842 contains pulse?by?pulse current limiting to protect the power switch and external components. when the peak of the switching current reaches the current limit, the power switch turns off after the current limit delay. the switch will not turn on until the next switching cycle. the current limit threshold is independent of switching duty cycle. the maximum load current, given by the following formula under continuous conduction mode, is less than the current limit due to the ripple current. i o(max) i lim v o (v in v o ) 2(l)(v in )(f s ) where: f s = switching frequency, i lim = current limit threshold, v o = output voltage, v in = input voltage, l = inductor value. when the regulator runs under current limit, the subharmonic oscillation may cause low frequency oscillation, as shown in figure 6. similar to current mode control, this oscillation occurs at the duty cycle greater than 50% and can be alleviated by using a larger inductor value. the current limit threshold is reduced to foldback current when the fb pin falls below foldback threshold. this feature protects the ic and external components under the power up or over?load conditions. figure 6. the regulator in current limit
ncv8842 http://onsemi.com 8 boost pin the boost pin provides base driving current for the power switch. a voltage higher than v in provides required headroom to turn on the power switch. this in turn reduces ic power dissipation and improves overall system efficiency. the boost pin can be c onnected to an external boost?strapping circuit which typically uses a 0.1 f capacitor and a 1n914 or 1n4148 diode, as shown in figure 1. when the power switch is turned on, the voltage on the boost pin is equal to v boost v in v o v f where: v f = diode forward voltage. the anode of the diode can be connected to any dc voltage as well as the regulated output voltage (figure 1). however, the maximum voltage on the boost pin shall not exceed 40 v. as shown in figure 7, the boost pin current includes a constant 7.0 ma pre?driver current and base current proportional to switch conducting current. a detailed discussion of this current is conducted in thermal consideration section. a 0.1 f capacitor is usually adequate for maintaining the boost pin voltage during the on time. figure 7. the boost pin current includes 7.0 ma pre?driver current and base current when the switch is turned on. the beta decline of the power switch further increases the base current at high switching current 0 0.5 1.0 1. 5 switching current (a) boost pin current (ma) 0 5 10 15 20 25 30 shutdown the internal power switch will not turn on until the v in pin rises above the startup voltage. this ensures no switching will occur until adequate supply voltage is provided to the ic. the ic enters a sleep mode when the shdnb pin is pulled below the shutdown threshold voltage. in sleep mode, the power switch is kept open and the supply current reduces to shutdown quiescent current ( 1 a typically). this pin has an internal pull?down current. when not in use, pull this pin up to v cc with a resistor (see figure 1). startup during power up, the regulator tends to quickly charge up the output capacitors to reach voltage regulation. this gives rise to an excessive in?rush current which can be detrimental to the inductor, ic and catch diode. in v 2 control , the compensation capacitor provides soft?start with no need for extra pin or circuitry. during the power up, the output source current of the error amplifier charges the compensation capacitor which forces v c pin and thus output voltage ramp up gradually. the soft?start duration can be calculated by t ss v c c comp i source where: v c = v c pin steady?state voltage, which is approximately equal to error amplifier?s reference voltage. c comp = compensation capacitor connected to the v c pin i source = output source current of the error amplifier. using a 0.1 f c comp , the calculation shows a t ss over 5.0 ms which is adequate to avoid any current stresses. figure 8 shows the gradual rise of the v c , v o and envelope of the v sw during power up. there is no voltage over?shoot after the output voltage reaches the regulation. if the supply voltage rises slower than the v c pin, output voltage may over?shoot. figure 8. the power up transition of ncv8842 regulator
ncv8842 http://onsemi.com 9 short circuit when the v fb pin voltage drops below foldback threshold, the regulator reduces the peak current limit by 40% and switching frequency to 1/4 of the nominal frequency. these features are designed to protect the ic and external components during over load or short circuit conditions. in those conditions, peak switching current is clamped to the current limit threshold. the reduced switching frequency significantly increases the ripple current, and thus lowers the dc current. the short circuit can cause the minimum duty cycle to be limited by minimum output pulse width. the foldback frequency reduces the minimum duty cycle by extending the switching cycle. this protects the ic from overheating, and also limits the power that can be transferred to the output. the current limit foldback effectively reduces the current stress on the inductor and diode. when the output is shorted, the dc current of the inductor and diode can approach the current limit threshold. therefore, reducing the current limit by 40% can result in an equal percentage drop of the inductor and diode current. the short circuit waveforms are captured in figure 9, and the benefit of the foldback frequency and current limit is self?evident. figure 9. in short circuit, the foldback current and foldback frequency limit the switching current to protect the ic, inductor and catch diode thermal considerations a calculation of the power dissipation of the ic is always necessary prior to the adoption of the regulator. the current drawn by the ic includes quiescent current, pre?driver current, and power switch base current. the quiescent current drives the low power circuits in the ic, which include comparators, error amplifier and other logic blocks. therefore, this current is independent of the switching current and generates power equal to w q v in i q where: i q = quiescent current. the pre?driver current is used to turn on/off the power switch and is approximately equal to 12 ma in worst case. during steady state operation, the ic draws this current from the boost pin when the power switch is on and then receives it from the v in pin when the switch is off. the pre?driver current always returns to the v sw pin. since the pre?driver current goes out to the regulator?s output even when the power switch is turned off, a minimum load is required to prevent overvoltage in light load conditions. if the boost pin voltage is equal to v in + v o when the switch is on, the power dissipation due to pre?driver current can be calculated by w drv 12 ma (v in v o v o 2 v in ) the base current of a bipolar transistor is equal to collector current divided by beta of the device. beta of 60 is used here to estimate the base current. the boost pin provides the base current when the transistor needs to be on. the power dissipated by the ic due to this current is w base v o 2 v in i s 60 where: i s = dc switching current. when the power switch turns on, the saturation voltage and conduction current contribute to the power loss of a non?ideal switch. the power loss can be quantified as w sat v o v in i s v sat where: v sat = saturation voltage of the power switch which is shown in figure 5. the switching loss occurs when the switch experiences both high current and voltage during each switch transition. this regulator has a 30 ns turn?off time and associated power loss is equal to w s i s v in 2 30 ns f s the turn?on time is much shorter and thus turn?on loss is not considered here. the total power dissipated by the ic is sum of all the above w ic w q w drv w base w sat w s the ic junction temperature can be calculated from the ambient temperature, ic power dissipation and thermal resistance of the package. the equation is shown as follows, t j w ic r ja t a minimum load requirement as pointed out in the previous section, a minimum load is required for this regulator due to the pre?driver current feeding the output. placing a resistor equal to v o divided by 12 ma should prevent any voltage overshoot at light load conditions. alternatively, the feedback resistors can be valued properly to consume 12 ma current.
ncv8842 http://onsemi.com 10 component selection input capacitor in a buck converter, the input capacitor witnesses pulsed current with an amplitude equal to the load current. this pulsed current and the esr of the input capacitors determine the v in ripple voltage, which is shown in figure 10. for v in ripple, low esr is a critical requirement for the input capacitor selection. the pulsed input current possesses a significant ac component, which is absorbed by the input capacitors. the rms current of the input capacitor can be calculated using: i rms i o d(1 d) where: d = switching duty cycle which is equal to v o /v in . i o = load current. figure 10. input voltage ripple in a buck converter to calculate the rms current, multiply the load current with the constant given by figure 11 at each duty cycle. it is a common practice to select the input capacitor with an rms current rating more than half the maximum load current. if multiple capacitors are paralleled, the rms current for each capacitor should be the total current divided by the number of capacitors. figure 11. input capacitor rms current can be calculated by multiplying y value with maximum load current at any duty cycle 0 0.2 0.4 1. 0 duty cycle 0 0.1 0.3 0.4 0.5 0.6 0.2 0.6 0.8 i rms (xi o ) selecting the capacitor type is determined by each design?s constraint and emphasis. the aluminum electrolytic capacitors are widely available at lowest cost. their esr and esl (equivalent series inductor) are relatively high. multiple capacitors are usually paralleled to achieve lower esr. in addition, electrolytic capacitors usually need to be paralleled with a ceramic capacitor for filtering high frequency noises. the os?con are solid aluminum electrolytic capacitors, and therefore has a much lower esr. recently, the price of the os?con capacitors has dropped significantly so that it is now feasible to use them for some low cost designs. electrolytic capacitors are physically lar ge, and not used in applications where the size, and especially height is the major concern. ceramic capacitors are now available in values over 10 f. since the ceramic capacitor has low esr and esl, a single ceramic capacitor can be adequate for both low frequency and high frequency noises. the disadvantage of ceramic capacitors are their high cost. solid tantalum capacitors can have low esr and small size. however, the reliability of the tantalum capacitor is always a concern in the application where the capacitor may experience surge current. output capacitor in a buck converter, the requirements on the output capacitor are not as critical as those on the input capacitor. the current to the output capacitor comes from the inductor and thus is triangular. in most applications, this makes the rms ripple current not an issue in selecting output capacitors. the output ripple voltage is the sum of a triangular wave caused by ripple current flowing through esr, and a square wave due to esl. capacitive reactance is assumed to be small compared to esr and esl. the peak to peak ripple current of the inductor is: i p p v o (v in v o ) (v in )(l)(f s ) v ripple(esr) , the output ripple due to the esr, is equal to the product of i p?p and esr. the voltage developed across the esl is proportional to the di/dt of the output capacitor. it is realized that the di/dt of the output capacitor is the same as the di/dt of the inductor current. therefore, when the switch turns on, the di/dt is equal to (v in ? v o )/l, and it becomes v o /l when the switch turns off. the total ripple voltage induced by esl can then be derived from v ripple(esl) esl( v in l ) esl( v in v o l ) esl( v in l ) the total output ripple is the sum of the v ripple(esr) and v ripple(esr) .
ncv8842 http://onsemi.com 11 figure 12. the output voltage ripple using two 10 f ceramic capacitors in parallel figure 13. the output voltage ripple using one 100 f poscap capacitor figure 14. the output voltage ripple using one 100 f os?con figure 15. the output voltage ripple using one 100 f tantalum capacitor figure 12 to figure 15 show the output ripple of a 5.0 v to 3.3 v/500 ma regulator using 22 h inductor and various capacitor types. at the switching frequency, the low esr and esl make the ceramic capacitors behave capacitively as shown in figure 12. additional paralleled ceramic capacitors will further reduce the ripple voltage, but inevitably increase the cost. ?poscap?, manufactured by sanyo, is a solid electrolytic capacitor. the anode is sintered tantalum and the cathode is a highly conductive polymerized organic semiconductor. tpc series, featuring low esr and low profile, is used in the measurement of figure 13. it is shown that poscap presents a good balance of capacitance and esr, compared with a ceramic capacitor. in this application, the low esr generates less than 5.0 mv of ripple and the esl is almost unnoticeable. the esl of the through?hole os?con capacitor give rise to the inductive impedance. it is evident from figure 14 which shows the step rise of the output ripple on the switch turn?on and large spike on the switch turn?off. the esl prevents the output capacitor from quickly charging up the parasitic capacitor of the inductor when the switch node is pulled below ground through the catch diode conduction. this results in the spike associated with the falling edge of the switch node. the d package tantalum capacitor used in figure 15 has the same footprint as the poscap, but doubles the height. the esr of the tantalum capacitor is apparently higher than the poscap. the electrolytic and tantalum capacitors provide a low?cost solution with compromised performance. the reliability of the tantalum capacitor is not a serious concern for output filtering because the output capacitor is usually free of surge current and voltage. diode selection the diode in the buck converter provides the inductor current path when the power switch turns off. the peak reverse voltage is equal to the maximum input voltage. the peak conducting current is clamped by the current limit of the ic. the average current can be calculated from: i d(avg) i o (v in v o ) v in
ncv8842 http://onsemi.com 12 the worse case of the diode average current occurs during maximum load current and maximum input voltage. for the diode to survive the short circuit condition, the current rating of the diode should be equal to the foldback current limit. see table 1 for schottky diodes from on semiconductor which are suggested for use with the ncv8842 regulator. inductor selection when choosing inductors, one might have to consider maximum load current, core and copper losses, component height, output ripple, emi, saturation and cost. lower inductor values are chosen to reduce the physical size of the inductor. higher value cuts down the ripple current, core losses and allows more output current. for most applications, the inductor value falls in the range between 2.2 h and 22 h. the saturation current ratings of the inductor shall not exceed the i l(pk) , calculated according to i l(pk) i o v o (v in v o ) 2(f s )(l)(v in ) the dc current through the inductor is equal to the load current. the worse case occurs during maximum load current. check the vendor?s spec to adjust the inductor value under current loading. inductors can lose over 50% of inductance when it nears saturation. the core materials have a significant effect on inductor performance. the ferrite core has benefits of small physical size, and very low power dissipation. but be careful not to operate these inductors too far beyond their maximum ratings for peak current, as this will saturate the core. powered iron cores are low cost and have a more gradual saturation curve. the cores with an open magnetic path, such as rod or barrel, tend to generate high magnetic field radiation. however, they are usually cheap and small. the cores providing a close magnetic loop, such as pot?core and toroid, generate low electro?magnetic interference (emi). there are many magnetic component vendors providing standard product lines suitable for the ncv8842. table 2 lists three vendors, their products and contact information. table 1. part number v breakdown (v) i average (a) v (f) (v) @ i average package 1n5817 20 1.0 0.45 axial lead 1n5818 30 1.0 0.55 axial lead 1n5819 40 1.0 0.6 axial lead mbr0520 20 0.5 0.385 sod?123 mbr0530 30 0.5 0.43 sod?123 mbr0540 40 0.5 0.53 sod?123 mbrs120 20 1.0 0.55 smb mbrs130 30 1.0 0.395 smb mbrs140 40 1.0 0.6 smb table 2. vendor product family web site telephone coiltronics uni?pac1/2: smt, barrel thin?pac: smt, toroid, low profile ctx: leaded, toroid www.coiltronics.com (516) 241?7876 coilcraft do1608: smt, barrel ds/dt 1608: smt, barrel, magnetically shielded do3316: smt, barrel ds/dt 3316: smt, barrel, magnetically shielded do3308: smt, barrel, low profile www.coilcraft.com (800) 322?2645 pulse ? www.pulseeng.com (619) 674?8100
ncv8842 http://onsemi.com 13 ordering information device package shipping ? NCV8842PWG so?16wep (pb?free) 47 units / rail ncv8842pwr2g so?16wep (pb?free) 1000 units / tape & reel ncv8842mnr2g dfn18 (pb?free) 2500 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv8842 http://onsemi.com 14 package dimensions soic 16?lead wide body exposed pad pw suffix case 751ag?01 issue o g ?w? ?u? p m 0.25 (0.010) w ?t? seating plane k d 16 pl c m 0.25 (0.010) t uw s s m f detail e detail e r x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable protrusion shall be 0.13 (0.005) total in excess of the d dimension at maximum material condition. 6. 751r?01 obsolete, new standard 751r?02. j m 14 pl pin 1 i.d. 8 1 16 9 top side 0.10 (0.004) t 16 exposed pad 18 back side l h dim a min max min max inches 10.15 10.45 0.400 0.411 millimeters b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc h 3.31 3.51 0.130 0.138 j 0.25 0.32 0.010 0.012 k 0.00 0.10 0.000 0.004 l 4.58 4.78 0.180 0.188 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 a b 9 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* .350 .175 .050 .376 .18 8 .200 .07 4 scale 2:1 .024 .145 exposed pad c l c l
ncv8842 http://onsemi.com 15 package dimensions 18?lead dfn, 5 x 6 mm mn suffix case 505?01 issue b c 0.15 e2 d2 l b 18x a d notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. e c e a b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 3.98 4.28 e 5.00 bsc e2 2.98 3.28 e 0.50 bsc k 0.20 ??? l 0.45 0.65 c 0.15 pin 1 location a1 (a3) seating plane c 0.08 c 0.10 18x k 18x a 0.10 b c 0.05 c note 3 19 10 18 2x 2x 18x side view top view bottom view on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?t ypicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license un der its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended f or surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in a ny manner. ncv8842/d v2 is a trademark of switch power, inc. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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